This invention relates to data buses, and particularly to controls for data buses used in integrated circuit chips and the like.
Data buses are used in integrated circuits (ICs) to transfer data between termination points established by the IC. Usually, one or more of the termination points is coupled to a master device, such as a user-controlled microprocessor, and other termination points are coupled to one or more slave devices that control peripheral devices, such as a memory or the like. To avoid overlapping data messages that may lead to error in data transmission between the master and slave devices, it is common to employ an arbiter to arbitrate transmission of messages on the bus. One such bus design is an Advanced High-performance Bus (AHB) from ARM Limited of Cambridge, England. The AHB bus design is a form of an Advanced Microcontroller Bus Architecture (AMBA) bus. The AHB bus provides high performance, high clock frequency transfer between multiple bus master devices and multiple bus slave devices through use of an arbiter. The AHB bus is particularly useful in integrated circuit chips, including single chip processors, to couple processors to on-chip memories and off-chip external memory interfaces.
The slave devices ordinarily operate external peripheral devices through device controllers. In most cases, commands are fed to the device controller by a command queue, which is a first-in, first-out (FIFO) register. The device controller pulls commands from the FIFO as the commands become available. The device controller often operates at a slower speed than the bus. Consequently, it is possible that the FIFO becomes filled with several commands.
One problem of many bus designs, including the AHB bus, is that it is not altogether possible to accurately follow a transaction over the bus, through the FIFO and to the device controller for maintenance or analysis (debugging) purposes. More particularly, where the bus runs at a speed faster than that of the device controller, the FIFO acts as a buffer containing several unexecuted commands in a queue. A maintenance command sent over the bus for analysis purposes might be delayed until commands ahead of it in the queue are processed by the device controller. Consequently a significant delay in the transaction may occur between issuing the maintenance command onto the bus and pulling the command up from the FIFO by the device controller.
To overcome this problem, it has been common to operate a single master device to issue one command at a time for analysis of the bus. This technique necessitated disabling all competing master devices from the bus. However, this technique did not accurately simulate operation of the bus. More particularly, an operating bus system employs several master devices that compete for use of the bus and for access to a slave device and its peripheral device. If all but one of the competing master devices is disabled, arbitration of access to the competing master devices cannot be analyzed.
The present invention is directed to a debug technique that slows operation of the slave unit so that a transaction on the bus can be easily traced for maintenance and analysis purposes without disabling competing master devices.
In one embodiment, the slave device receives commands from a master device and places them in a queue for execution on a first-in, first-out basis. A status register is responsive to the command queue to provide a first command signal when the command queue is full of commands and a second command signal when the command queue is not empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control is responsive to the DEBUG and the first and second status signals to provide a queue full signal in response to either (1) the first status signal or (2) both the DEBUG and the second status signals to operate the data bus to a predetermined mode. In preferred embodiments, the predetermined mode is either a split mode that denies a requesting master device access to the data bus and idles the bus, or a stall mode that stalls the bus. Maintenance commands are processed through the data bus and slave device one at a time to permit analysis of the performance of the system.
In another embodiment the status register identifies whether the data FIFO is full and not empty and the bus control operates the data bus to the predetermined mode when the data FIFO is full or in response to the DEBUG mode when the data FIFO is not empty.
In yet other embodiments, the status of both the command queue and the data FIFO is employed to operate the bus control.